The present invention pertains to a phase comparison circuit for a PLL circuit used to regenerate a clock signal from EFM data or other encoded data for a phase comparison circuit, such as a data reproduction device for CD or DVD or a receiver of an ISDN data transmission device.
In a data reproduction device for CD or DVD, a PLL circuit is used to regenerate a clock signal from EFM modulated data obtained by means of an optical detection circuit. Similarly, a PLL circuit is used on the receiver side of an ISDN data transmitting device in order to regenerate a clock signal based on the received encoded data. In either case, the PLL is provided with a phase comparison circuit for phase comparison.
Clock signals are generated by respective data reproduction devices for CD such that the maximum read cycle of EFM data becomes 11 times the regenerated clock signal, and for DVD, the maximum read cycle of EFM data becomes 14 times the regenerated clock signal.
In general, at the PLL circuit, after the clock signal generated by means of a voltage control oscillator (VCO) is divided at a prescribed dividing ratio using a frequency divider, comparison of the frequency or phase with that of the read EFM data is performed. According to the result of the comparison of frequency or phase, a control signal reflecting the error is generated in order to control the frequency and the phase of the signal oscillated by the VCO, so that a clock signal having a specific frequency and phase can be regenerated. In addition, the regenerated clock signal is used, for example, as a clock signal for DSP signal processing.
Because the phase comparison circuit in the PLL circuit of the aforementioned conventional data reproduction device generates a pulse having both positive and negative polarities corresponding to phase difference, and the signal obtained through the integration of said pulse signal is used as the control signal of VCO, there is a disadvantage that the reply (response) of the PLL circuit is slow. In the case of the reproduction device of a high-speed CD or a DVD, a high-speed response is necessary, and the phase comparison circuit in the PLL circuit of the current reproduction device needs to be improved.
The present invention was made in the light of this circumstance, and its purpose is to present a phase comparison circuit capable of realizing high-speed response of the PLL circuit and high-speed regeneration of signals.
In order to achieve the aforementioned purpose, the phase comparison circuit of the present invention has a delay circuit that adds a prescribed delay time of either a first or a second value to an input signal in order to output a delayed signal, a first edge detection circuit that outputs a first edge detection signal upon detecting the changing edge at which the aforementioned input signal changes from the first level to the second level, a second edge detection circuit that outputs a second edge detection signal upon detecting the changing edge at which the aforementioned input signal changes from the second level to the first level, a phase detection circuit that outputs a first control signal by comparing the phase of the aforementioned delayed signal and the phase of a clock signal when the aforementioned first detection signal is output and outputs a second control signal by comparing the phase of the aforementioned delayed signal and the phase of a clock signal when the aforementioned second detection signal is output, and an output circuit that outputs a phase difference signal indicating the phase difference between the aforementioned delayed signal and the aforementioned clock signal according to the aforementioned first and the second control signals.
In addition, the phase comparison circuit of the present invention has a delay circuit that adds a prescribed delay time of either a first or a second value to an input signal in order to output a delayed signal, a first edge detection circuit that outputs a first edge detection signal upon detecting the changing edge at which the aforementioned input signal changes from the first level to the second level, a second edge detection circuit that outputs a second edge detection signal upon detecting the changing edge at that the aforementioned input signal changes from the second level to the first level, a control circuit which receives the aforementioned delayed signal and the aforementioned first and second edge detection signals and outputs a phase information signal corresponding to said signals, a phase detection circuit that outputs a first and a second control signal by comparing the phase of the aforementioned phase information signal and the phase of the clock signal, and an output circuit that outputs a phase difference signal indicating the phase difference between the aforementioned delayed signal and the aforementioned clock signal according to the aforementioned first and second control signal.
In addition, the present invention preferably controls the frequency of the aforementioned clock signal and the aforementioned delay time according to the aforementioned phase difference signal. Also, control is performed in such a way that the aforementioned delay time becomes shorter as the frequency of the aforementioned clock signal becomes higher.
Furthermore, the present invention preferably holds the aforementioned phase difference signal at a first level corresponding to the aforementioned first control signal and at a second level corresponding to the aforementioned second control signal. Moreover, the aforementioned phase difference signal enters a high-impedance state when the aforementioned delayed signal and the aforementioned clock signal are synchronous.
In the present invention, changing edges of the input signal are detected by the first and second edge detection circuits, and a first and second edge detection signal are output, respectively. In addition, a delayed signal, for which a prescribed delay time is added to an input signal, is output by the delay circuit. Phase of the aforementioned delayed signal and the phase of the clock signal are compared by the phase comparison circuit when a change has occurred in the aforementioned input signal, that is, when the aforementioned first or the second edge detection signal is output, and a first and second signal are output according to the result of said comparison. Furthermore, a phase difference signal indicating the phase difference between the aforementioned delayed signal and the aforementioned clock signal is output from the output circuit according to the control signals. For example, a positive pulse is generated for the phase difference signal when the phase of the aforementioned delayed signal is ahead of that of the aforementioned clock signal; and, on the contrary, a negative pulse is generated for the phase difference signal when the phase of the aforementioned delayed signal is behind that of the aforementioned clock signal. In addition, when the phases of the aforementioned delayed signal and the aforementioned clock signal are synchronous, the aforementioned phase difference signal is held at a high-impedance state.
The aforementioned clock signal is obtained from the output signal from the voltage control oscillation circuit whose oscillation frequency corresponds to the aforementioned phase difference signal, and frequency of the aforementioned clock signal is controlled according to the aforementioned input signal. Because the PLL circuit configured with this kind of phase comparison circuit has a good response characteristic and is capable of responding quickly to the input signal, for example, high-speed reproduction of recorded data can be achieved in a CD or a DVD reproduction device.